1. Technical Field
This disclosure relates generally to zero keeper circuits and, more particularly, to zero keeper circuits configured for design-for-test (DFT) coverage, methods for controlling such a zero keeper circuit, devices that include such a zero keeper circuit, and memory apparatus that include such a zero keeper circuit.
2. Description of the Related Art
A zero keeper circuit, also referred to as a dynamic to static converter, is a circuit configured to receive a dynamic signal and convert the dynamic signal to a static signal. An output of zero keeper circuit may be coupled to critical logic. Designers may desire to scan such logic with design-for-test (DFT) techniques. In typical configurations, however, the output of a zero keeper circuit can be set to only a single value, either a logic high or a logic low. If, for example, a zero keeper circuit output is coupled to an OR gate and can be set only to a logic high, DFT coverage is lost for the downstream logic. If, in another example, a zero keeper circuit output is coupled to an AND gate and can only be set to a logic low, DFT coverage is again is lost for the downstream logic. Although an inverter may be placed at the output of the zero keeper, just before the AND or OR gate to reverse the polarity of the zero keeper output signal, additional logic introduced in the output path results in a loss of speed of transitioning signals.